Through-silicon vias (TSVs) are the latest cutting-edge chip-to-chip interconnection techniques for creating vertical interconnects between chips and between wafers. TSVs have a number of advantages including small package sizes, fast signal transmission and low power consumption.
Edge defects that can be found in standard wafers from TSV processes include: non-concentricity due to bonding misalignment; edge wears; presence of scribes; sputtered metal or insulating coating material on wafer surface; and wafer warpage. There are also notch defects including incomplete cuts, damage, meal or adhesive clogging or covering, presence of metal lines, etc. Due to significant morphological deteriorations of wafer notches, in production lines in the world employing the currently popular TSV packaging technology, aligners are used for the exposure of TSV wafers (notched wafers), which is accomplished based on marks for manual alignment without taking into account the notches. However, the conventional pre-alignment methods for TSV wafers are associated with a number of problems such as, for example, being low in efficiency, having a pre-alignment accuracy that is low and vulnerable to human disturbance, and not allowing automation.
Apart from the pre-alignment of TSV wafers, there are also practical needs for the positioning of wafers from various processes, such as warped wafers, ultra-thin wafer and Taiko wafers. However, as wafers from different processes pose different challenges in terms of centering and orientation, how to provide a pre-alignment device adapted to the handling of wafers from multiple processes including warped wafers, ultra-thin wafer and Taiko wafers remains an urgent task for those skilled in the art.